# The cad/abc port

## abc-1.01.20210519 – system for sequential logic synthesis and verification

## Description

    ABC is a growing software system for synthesis and verification of binary
    sequential logic circuits appearing in synchronous hardware designs. ABC
    combines scalable logic optimization based on And-Inverter Graphs (AIGs),
    optimal-delay DAG-based technology mapping for look-up tables and standard
    cells, and innovative algorithms for sequential synthesis and verification.

WWW: https://people.eecs.berkeley.edu/~alanmi/abc

Only for arches
  aarch64 aarch64 alpha alpha amd64 amd64 arm arm hppa hppa i386 i386 mips64 mips64 mips64el mips64el powerpc powerpc powerpc64 powerpc64 riscv64 riscv64 sh sparc64 sparc64
Categories:
  cad

## Library dependencies

- STEM->=8,<9:lang/gcc/8,-libs

## Build dependencies

- STEM->=8,<9:lang/gcc/8
- STEM->=8,<9:lang/gcc/8,-c++
- devel/cmake/core
- devel/gmake
- devel/ninja

## Run dependencies