Ð þí3—8/¤(ó/lAries Embedded M100PFEVPS !aries,m100pfsevpmicrochip,mpfscpus,B@cpu@0 !sifive,e51sifive,rocket0riscv?cpuK@^€k@x |rv64imac†rv64i$•imaczicntrzicsrzifenceizihpmª ±disabled¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@1#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@2#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@3#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@4#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸcpu-mapcluster0core0ccore1ccore2ccore3ccore4cmssrefclk !fixed-clockgtsY@¸syscontroller!microchip,mpfs-sys-controller„±okaymssclkclk !fixed-clockgtÄ´¸soc !simple-bus‹cache-controller@20100005!microchip,mpfs-ccachesifive,fu540-c000-ccachecachexM@’`m ž¬ ½¸clint@2000000&!sifive,fu540-c000-clintsifive,clint0xÀPÈ        interrupt-controller@c000000)!sifive,fu540-c000-plicsifive,plic-1.0.0x ÀÑHÈ   ܺ¸ dma-controller@3000000!!microchip,mpfs-pdmasifive,pdma0x€¬  ½ çôsyscon@200020000!microchip,mpfs-mss-top-sysregsysconsimple-mfdx ÿ¸syscon@20003000!!microchip,mpfs-sysreg-scbsysconx 0clock-controller@38010000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38040000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38100000!microchip,mpfs-ccc@x88 99 g ±disabledclock-controller@38400000!microchip,mpfs-ccc@x8@8€9@9€g ±disabledserial@20000000 !ns16550ax  ¬ ½Z#ª ±disabledserial@20100000 !ns16550ax  ¬ ½[#ª ±okayserial@20102000 !ns16550ax   ¬ ½\#ª ±okayserial@20104000 !ns16550ax @ ¬ ½]#ª ±okayserial@20106000 !ns16550ax ` ¬ ½^ª #±okaymmc@20008000 !microchip,mpfs-sd4hccdns,sd4hcx €¬ ½Xª1úð€±okay?I[lu‚�œªspi@20108000!microchip,mpfs-spix €¬ ½6ª ±okayspi@20109000!microchip,mpfs-spix �¬ ½7ª±okayspi@21000000.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x!¬ ½Uª±okayi2c@2010a000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x  ¬ ½:ªt† ±okayi2c@2010b000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x °¬ ½=ªt† ±okaycan@2010c000!microchip,mpfs-canx Àª%¬ ½8µ±okaycan@2010d000!microchip,mpfs-canx Ъ%¬ ½9µ ±disabledethernet@20110000!microchip,mpfs-macbcdns,macbx  ¬ ½@ABCDE¼ª Îpclkhclkµ±okayÚgmiiãethernet-phy@0x¸ethernet@20112000!microchip,mpfs-macbcdns,macbx  ¬ ½FGHIJK¼ª Îpclkhclkµ±okayÚgmiiãethernet-phy@0x¸gpio@20120000!microchip,mpfs-gpiox ¬ ÑÀªîþ±okay8½  pmic-irq-hog mmc-sel-hog  gpio@20121000!microchip,mpfs-gpiox ¬ ÑÀªîþ ±disabledgpio@20122000!microchip,mpfs-gpiox  ¬ ÑÀªîþ±okay€½  !"#$%&'()*+,rtc@20124000!microchip,mpfs-rtcx @¬ ½PQª! Îrtcrtcref±okayusb@20201000!microchip,mpfs-musbx ¬ ½VWª,dmamc±okayªg¸fabric-clk3 !fixed-clockgt¹¬ ¸fabric-clk1 !fixed-clockgtsY@¸pcie@2000000000!microchip,pcie-host-1.0À?pci0x C€ C  PcfgbridgectrlZ¬ ½w`drª Îfic0fic3‹ €…�±okay¸interrupt-controllerÀѸaliasesŸ/soc/ethernet@20110000©/soc/ethernet@20112000³/soc/serial@20000000»/soc/serial@20100000Ã/soc/serial@20102000Ë/soc/serial@20104000Ó/soc/serial@20106000Û/soc/gpio@20120000á/soc/gpio@20122000chosençserial1:115200n8memory@80000000?memoryx€@memory@1040000000?memoryx@@ #address-cells#size-cellsmodelcompatibletimebase-frequencydevice_typei-cache-block-sizei-cache-setsi-cache-sizeregriscv,isariscv,isa-baseriscv,isa-extensionsclocksstatusphandle#interrupt-cellsinterrupt-controllerd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitnext-level-cachecpu#clock-cellsclock-frequencymboxesrangescache-levelcache-unifiedinterrupt-parentinterruptsinterrupts-extendedriscv,ndevdma-channels#dma-cells#reset-cellsreg-io-widthreg-shiftcurrent-speedmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedno-1-8-vsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpresetslocal-mac-addressclock-namesphy-modephy-handlegpio-controller#gpio-cellsngpiosgpio-hoginputoutput-highinterrupt-namesdr_mode#mbox-cellsreg-namesbus-rangeinterrupt-mapinterrupt-map-maskmsi-parentmsi-controllerethernet0ethernet1serial0serial1serial2serial3serial4gpio0gpio1stdout-path