36 #ifndef ATMEGA_128RFA1_H
37 #define ATMEGA_128RFA1_H (1)
51 #define RG_TRX_STATUS (0x1)
53 #define SR_CCA_DONE 0x1,0x80,7
55 #define SR_CCA_STATUS 0x1,0x40,6
57 #define SR_TRX_STATUS 0x1,0x1f,0
59 #define RG_TRX_STATE (0x2)
61 #define SR_TRAC_STATUS 0x2,0xe0,5
63 #define SR_TRX_CMD 0x2,0x1f,0
65 #define RG_TRX_CTRL_0 (0x3)
67 #define SR_PAD_IO 0x3,0xe0,5
69 #define SR_PAD_IO_CLKM 0x3,0x10,4
83 #define SR_CLKM_SHA_SEL 0x3,0x8,3
85 #define SR_CLKM_CTRL 0x3,0x7,0
87 #define CLKM_no_clock (0)
102 #define CLKM_16MHz (5)
105 #define RG_TRX_CTRL_1 (0x4)
107 #define SR_PA_EXT_EN 0x4,0x80,7
109 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
111 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
113 #define SR_RX_BL_CTRL 0x4,0x10,4
115 #define SR_SPI_CMD_MODE 0x4,0xc,2
117 #define SR_IRQ_POLARITY 0x4,0x1,0
119 #define SR_IRQ_MASK_MODE 0x4,0x2,1
121 #define RG_PHY_TX_PWR (0x5)
123 #define SR_PA_BUF_LT 0x5,0xc0,6
125 #define SR_PA_LT 0x5,0x30,4
127 #define SR_TX_PWR 0x5,0xf,0
129 #define RG_PHY_RSSI (0x6)
131 #define SR_RX_CRC_VALID 0x6,0x80,7
133 #define SR_RND_VALUE 0x6,0x60,5
135 #define SR_RSSI 0x6,0x1f,0
137 #define RG_PHY_ED_LEVEL (0x7)
139 #define SR_ED_LEVEL 0x7,0xff,0
141 #define RG_PHY_CC_CCA (0x8)
143 #define SR_CCA_REQUEST 0x8,0x80,7
145 #define SR_CCA_MODE 0x8,0x60,5
147 #define SR_CHANNEL 0x8,0x1f,0
149 #define RG_CCA_THRES (0x9)
151 #define SR_CCA_ED_THRES 0x9,0xf,0
153 #define RG_RX_CTRL (0xa)
155 #define SR_PDT_THRES 0xa,0xf,0
157 #define RG_SFD_VALUE (0xb)
159 #define SR_SFD_VALUE 0xb,0xff,0
161 #define RG_TRX_CTRL_2 (0xc)
163 #define SR_RX_SAFE_MODE 0xc,0x80,7
165 #define SR_OQPSK_DATA_RATE 0xc,0x3,0
167 #define RG_ANT_DIV (0xd)
169 #define SR_ANT_SEL 0xd,0x80,7
171 #define SR_ANT_DIV_EN 0xd,0x8,3
173 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
175 #define SR_ANT_CTRL 0xd,0x3,0
177 #define RG_IRQ_MASK (0xe)
179 #define SR_MASK_BAT_LOW 0xe,0x80,7
181 #define SR_MASK_TRX_UR 0xe,0x40,6
183 #define SR_MASK_AMI 0xe,0x20,5
185 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
187 #define SR_MASK_TRX_END 0xe,0x8,3
189 #define SR_MASK_TRX_START 0xe,0x4,2
191 #define SR_MASK_PLL_LOCK 0xe,0x1,0
193 #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
195 #define RG_IRQ_STATUS (0xf)
197 #define SR_BAT_LOW 0xf,0x80,7
199 #define SR_TRX_UR 0xf,0x40,6
201 #define SR_AMI 0xf,0x20,5
203 #define SR_CCA_ED_READY 0xf,0x10,4
205 #define SR_RX_END 0xf,0x8,3
207 #define SR_RX_START 0xf,0x4,2
209 #define SR_PLL_LOCK 0xf,0x1,0
211 #define SR_PLL_UNLOCK 0xf,0x2,1
213 #define RG_VREG_CTRL (0x10)
215 #define SR_AVREG_EXT 0x10,0x80,7
217 #define SR_AVDD_OK 0x10,0x40,6
219 #define SR_DVREG_EXT 0x10,0x8,3
221 #define SR_DVDD_OK 0x10,0x4,2
223 #define RG_BATMON (0x11)
225 #define SR_BATMON_OK 0x11,0x20,5
227 #define SR_BATMON_HR 0x11,0x10,4
229 #define SR_BATMON_VTH 0x11,0xf,0
231 #define RG_XOSC_CTRL (0x12)
233 #define SR_XTAL_MODE 0x12,0xf0,4
235 #define SR_XTAL_TRIM 0x12,0xf,0
237 #define RG_RX_SYN (0x15)
239 #define SR_RX_PDT_DIS 0x15,0x80,7
241 #define SR_RX_PDT_LEVEL 0x15,0xf,0
243 #define RG_XAH_CTRL_1 (0x17)
245 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
247 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
249 #define SR_AACK_ACK_TIME 0x17,0x4,2
251 #define SR_AACK_PROM_MODE 0x17,0x2,1
253 #define RG_FTN_CTRL (0x18)
255 #define SR_FTN_START 0x18,0x80,7
257 #define RG_PLL_CF (0x1a)
259 #define SR_PLL_CF_START 0x1a,0x80,7
261 #define RG_PLL_DCU (0x1b)
263 #define SR_PLL_DCU_START 0x1b,0x80,7
265 #define RG_PART_NUM (0x1c)
267 #define SR_PART_NUM 0x1c,0xff,0
268 #ifndef RFA1_PART_NUM
269 #define RFA1_PART_NUM (131)
272 #define RG_VERSION_NUM (0x1d)
274 #define SR_VERSION_NUM 0x1d,0xff,0
275 #ifndef RFA1_VERSION_NUM_NONE
276 #define RFA1_VERSION_NUM_NONE (0)
278 #ifndef RFA1_VERSION_NUM_A
279 #define RFA1_VERSION_NUM_A (2)
281 #ifndef RFA1_VERSION_NUM_B
282 #define RFA1_VERSION_NUM_B (2)
284 #ifndef RFA1_VERSION_NUM_C
285 #define RFA1_VERSION_NUM_C (3)
287 #ifndef RFA1_VERSION_NUM_D
288 #define RFA1_VERSION_NUM_D (4)
291 #define RG_MAN_ID_0 (0x1e)
293 #define SR_MAN_ID_0 0x1e,0xff,0
295 #define RG_MAN_ID_1 (0x1f)
297 #define SR_MAN_ID_1 0x1f,0xff,0
299 #define RG_SHORT_ADDR_0 (0x20)
301 #define SR_SHORT_ADDR_0 0x20,0xff,0
303 #define RG_SHORT_ADDR_1 (0x21)
305 #define SR_SHORT_ADDR_1 0x21,0xff,0
307 #define RG_PAN_ID_0 (0x22)
309 #define SR_PAN_ID_0 0x22,0xff,0
311 #define RG_PAN_ID_1 (0x23)
313 #define SR_PAN_ID_1 0x23,0xff,0
315 #define RG_IEEE_ADDR_0 (0x24)
317 #define SR_IEEE_ADDR_0 0x24,0xff,0
319 #define RG_IEEE_ADDR_1 (0x25)
321 #define SR_IEEE_ADDR_1 0x25,0xff,0
323 #define RG_IEEE_ADDR_2 (0x26)
325 #define SR_IEEE_ADDR_2 0x26,0xff,0
327 #define RG_IEEE_ADDR_3 (0x27)
329 #define SR_IEEE_ADDR_3 0x27,0xff,0
331 #define RG_IEEE_ADDR_4 (0x28)
333 #define SR_IEEE_ADDR_4 0x28,0xff,0
335 #define RG_IEEE_ADDR_5 (0x29)
337 #define SR_IEEE_ADDR_5 0x29,0xff,0
339 #define RG_IEEE_ADDR_6 (0x2a)
341 #define SR_IEEE_ADDR_6 0x2a,0xff,0
343 #define RG_IEEE_ADDR_7 (0x2b)
345 #define SR_IEEE_ADDR_7 0x2b,0xff,0
347 #define RG_XAH_CTRL_0 (0x2c)
349 #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
351 #define SR_SLOTTED_OPERATION 0x2c,0x1,0
353 #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
355 #define RG_CSMA_SEED_0 (0x2d)
357 #define SR_CSMA_SEED_0 0x2d,0xff,0
359 #define RG_CSMA_SEED_1 (0x2e)
361 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
363 #define SR_AACK_SET_PD 0x2e,0x20,5
365 #define SR_AACK_DIS_ACK 0x2e,0x10,4
367 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
369 #define SR_CSMA_SEED_1 0x2e,0x7,0
371 #define RG_CSMA_BE (0x2f)
373 #define SR_MAX_BE 0x2f,0xf0,4
375 #define SR_MIN_BE 0x2f,0xf,0
377 #define RADIO_NAME "ATmega128RFA1"
379 #define RADIO_PART_NUM (RFA1_PART_NUM)
381 #if RADIO_TYPE == RADIO_ATMEGA128RFA1_A
382 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_A)
383 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_B
384 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_B)
385 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_C
386 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_C)
387 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_D
388 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_D)
393 #define TRX_REGISTER_BASEADDR (0x140)
395 #define AES_REGISTER_BASEADDR (0x13c)
398 #define TRX_IF_RFA1 (1)
400 #define TRX_CMD_RADDR_MASK (0x3f)
403 #define TRX_RESET_TIME_US (6)
406 #define TRX_INIT_TIME_US (510)
409 #define TRX_PLL_LOCK_TIME_US (180)
413 #define TRX_CCA_TIME_US (140)
416 #define TRX_IRQ_PLL_LOCK _BV(0)
419 #define TRX_IRQ_PLL_UNLOCK _BV(1)
422 #define TRX_IRQ_RX_START _BV(2)
425 #define TRX_IRQ_RX_END _BV(3)
428 #define TRX_IRQ_CCA_ED _BV(4)
431 #define TRX_IRQ_AMI _BV(5)
434 #define TRX_IRQ_TX_END _BV(6)
437 #define TRX_MIN_CHANNEL (11)
440 #define TRX_MAX_CHANNEL (26)
443 #define TRX_NB_CHANNELS (16)
449 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
451 #define TRX_SUPPORTS_BAND_2400 (1)
456 #define TRX_SUPPORTED_PAGES (42)
459 #define TRX_OQPSK250 (0)
462 #define TRX_OQPSK500 (1)
465 #define TRX_OQPSK1000 (2)
467 #define TRX_OQPSK2000 (3)
469 #define TRX_NONE (255)
475 extern volatile uint8_t SHADOW_IRQ_MASK;
476 static inline void disable_all_trx_irqs(
void)
478 SHADOW_IRQ_MASK = IRQ_MASK;
482 static inline void enable_all_trx_irqs(
void)
484 static bool already_shadowed = 0;
485 if (already_shadowed == 0)
488 SHADOW_IRQ_MASK = IRQ_MASK;
489 already_shadowed = 1;
496 SHADOW_IRQ_MASK = IRQ_MASK;
501 IRQ_MASK = SHADOW_IRQ_MASK;